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New posts in x86

MSVC: Invalid memcpy optimization?

c++ visual-c++ x86 memcpy compiler-bug

How can I load values from memory without polluting the cache?

assembly caching x86

How are MMIO, IO and PCI configuration request routed and handled by the OS in a NUMA system?

io x86 cpu-architecture numa

64-bit registers under 32-bit windows

assembly x86 x86-64

Vectorizing with unaligned buffers: using VMASKMOVPS: generating a mask from a misalignment count? Or not using that insn at all

gcc assembly x86 sse avx

Why does GCC drop the frame pointer on 64-bit?

gcc assembly x86 64-bit stack-frame

How to produce a minimal BIOS hello world boot sector with GCC that works from a USB stick on real hardware?

assembly x86 qemu gnu-assembler bare-metal

Is there any hope to call a common base class method on a std::variant efficiently?

c++ performance x86 c++17 variant

What happens when a mov instruction causes a page fault with interrupts disabled on x86?

linux-kernel x86 linux-device-driver interrupt page-fault

Which 2's complement integer operations can be used without zeroing high bits in the inputs, if only the low part of the result is wanted?

assembly binary x86 integer twos-complement

Is the TLB shared between multiple cores?

caching x86 cpu-architecture cpu-cache tlb

Why does this difference in asm matter for performance (in an un-optimized ptr++ vs. ++ptr loop)?

c++ performance loops assembly x86

How many pipeline stages does the Intel Core i7 have? [duplicate]

x86 pipeline

Running 32 bit assembly code on a 64 bit Linux & 64 bit Processor : Explain the anomaly

linux assembly gdb x86 x86-64

CPU cache behaviour/policy for file-backed memory mappings?

c++ x86 operating-system cpu-architecture cpu-cache

Shift a __m128i of n bits

c x86 sse simd sse2

What is the difference between assembly on mac and assembly on linux?

macos gcc assembly x86 x86-64

What is the stack engine in the Sandybridge microarchitecture?

assembly x86 intel cpu-architecture

How can the L1, L2, L3 CPU caches be turned off on modern x86/amd64 chips?

x86 intel cpu-cache memory-access msr

Understanding the impact of lfence on a loop with two long dependency chains, for increasing lengths

performance assembly x86 cpu-architecture perf
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