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New posts in cpu-architecture

About Adaptive Mode for L1 Cache in Hyper-threading

Out-of-order instruction execution: is commit order preserved?

How to tell length of an x86-64 instruction opcode using CPU itself?

How do Intel CPUs that use the ring bus topology decode and handle port I/O operations

Where does the scheduler run?

The inner workings of Spectre (v2)

Why doesn't Ice Lake have MOVDIRx like tremont? Do they already have better ones?

Assembly why is "lea eax, [eax + eax*const]; shl eax, eax, const;" combined faster than "imul eax, eax, const" according to gcc -O2?

Why is my C++ app faster than my C app (using the same library) on a Core i7

How does the branch predictor know if it is not correct?

Using System.getProperty("os.arch") to check if it is armeabi cpu

android cpu-architecture

ARM Cortex-M exception entry and stack framing

LFENCE is really useless vs. Spectre #2?

What are function epilogues and prologues?

Advantages of a 64 bit system

Lightweight method to use Amd64 instructions under 32-bit Windows?

How does 32-bit address 4GB if 2³² bits = 4 Billion bits not Bytes?

x86-64 usage of LFENCE

Who Decides Between I/O Mapped and Memory Mapped I/O (x86)

Why are there so many CPU architectures: x86, x64, x87, etc...?

cpu-architecture