Logo Questions Linux Laravel Mysql Ubuntu Git Menu
HTML CSS JAVASCRIPT SQL PYTHON PHP BOOTSTRAP JAVA JQUERY R React Kotlin
 

New posts in assembly

Can I pop from the middle of a stack?

assembly x86 callstack abi red-zone

Does a zero change jump on x86 clear the instruction prefetch queue?

assembly x86

When should I use size directives in x86?

assembly x86 x86-64 directive

Why is there two sequential move to EAX under optimization build?

delphi assembly optimization delphi-10.2-tokyo

how to get address of variable and dereference it in nasm x86 assembly?

pointers assembly x86 nasm

How does xchg work in Intel Assembly Language

assembly x86

What does __asm volatile ("pause" ::: "memory"); do?

c++ assembly parallel-processing x86 inline-assembly

How do I link a C++ subroutine to an x86 assembly program?

c++ gcc assembly x86 nasm

Web Assembly (Wasm), garbage collection

performance assembly garbage-collection webassembly

DMB instructions in an interrupt-safe FIFO

c gcc assembly c11 atomic

What does movslq do?

assembly x86-64 att sign-extension

Intel IACA analyzer alters assembly?

assembly simd avx2 iaca

How to properly setup SS, BP and SP in x86 Real Mode?

assembly x86 callstack bios

Is it worse in any aspect to use the CMPXCHG instruction on an 8-bit field than on a 32-bit field?

c assembly x86 c11 instruction-set

What does 'REX' stand for in an x86-64 REX prefix?

assembly x86 x86-64 intel machine-code

Why BIOS need to compare a value in (seemly) randomized address to zero in the second instruction?

assembly x86 qemu bios osdev

Mixed destination/source operand order in RISC-V assembly syntax

assembly riscv

Optimizing an incrementing ASCII decimal counter in video RAM on 7th gen Intel Core

assembly optimization x86 intel bootloader

Where to get the I/O port addresses assignment for hardware?

assembly io x86 hardware

Loop takes more cycles to execute than expected in an ARM Cortex-A72 CPU

performance assembly optimization arm neon
« Newer Entries Older Entries »