What does " ref " mean in systemverilog?

Question

I found this in systemverilog:

task automatic xxx(ref xxxpackage bus,input interface ift);

I want to know the usage of ref. What is the advantage?

Answer 1

Normally, task and function arguments declared as input are copied by value upon entry to the routine, and arguments declared as output are copied by value upon returning from the routine. inout arguments are copied both upon entry and return from the routine. Arguments declared with ref are not copied but instead are references to the actual arguments used when making the call to the routine. There are much stricter data type compatibility rules when using ref arguments.

In a task that consumes time, a ref can be used instead of an inout to capture value changes that occur while the task is active. Remember that an inout argument is copied into the task when it is called, and copied out when the task returns. Here is an example that you should try.

module top;
logic A,B;
task automatic mytask(inout logic arg1, ref logic arg2);
  #0 $display("%m %t arg1 %b arg2 %b",$time,arg1,arg2);
  // actual arguments have been set to 0
  #5 $display("%m %t arg1 %b arg2 %b",$time,arg1,arg2);
  #0 arg1 = 1; arg2 = 1;
  #5 $display("%m %t arg1 %b arg2 %b",$time,arg1,arg2);
endtask
initial #1 mytask(A,B);
initial begin
       A = 'z; B ='z;
       #2 A = 0; B = 0; // after call 
       // arguments have been set to 1
       #5 $display("%m %t A %b B %b",$time,A ,B);
       #5 $display("%m %t A %b B %b",$time,A ,B);
end
endmodule

See the difference between the inout and pass by ref arguments.

Note that a class variable is a reference to a class handle already, so passing a class variable by reference rarely has any benefit. Also, in a function, the only benefit of a ref argument might be performance in passing large data structures like an array instead of using an input, output, or inout.