How to emulate $display using Verilog Macros?

Question

I want to create a macro with multiple parameters just like $display.

My code looks like this but it doesn't work.

               `define format_macro(A) \
                      $write("%s", $sformatf(A)); \

This is how I called format_macro.

               `format_macro("variable = %d", variable)

How can I do this?

Answer 1

I want to create a macro with multiple parameters just like $display.

You can't. Verilog and SystemVerilog do not support variadic macros.

Here is a workaround if your goal is to use this for formatting strings or output, and you want to avoid having to type $sformat all over the place. You can define the macro to have a single argument, and combine that argument with $sformat. The caveat with doing this is that you must wrap the argument in parentheses when using the macro.

Note the ()'s for $sformatf are not part of the macro:

`define format_macro(A) \
        $write("%s", $sformatf A ); \

Then you can do this:

  `format_macro(("a = %d", a))
  `format_macro(("a = %d, b = %d", a, b))

BTW, there is an excellent screencast here which shows how to customize messaging in UVM. In it, the author shows this macro technique, along with some other nice tips if you're using UVM.

Answer 2

You are passing 2 arguments to your macro, "variable = %d" and variable, the macro only has 1 input defined. Reading the question it might not be multiple arguments that you want but a variable number.

For a static list either have macro setup to format the text:

`define say(n) $display("cowsay : %s", n);

initial begin
  `say("Moo")
end
=>cowsay : moo

Or create the string first and pass as a single argument.

`define say(n) $display("%s", n);

string msg;

initial begin 
  $sformat(msg, "variable is : %d", 3);
  `say(msg)
end
=>variable is :           3