What does a single quote (') mean in SystemVerilog?

Question

In an OVM example class, I see the following statement in the constructor:

void'(get_config_int("num_packets", this.num_packets));

What is the first part void'( supposed to be doing in this statement?

Answer 1

In this case the single quote is used for type casting. The void'() in void'(get_config_int("num_packets", this.num_packets)); means to ignore the return value from get_config_int.

A good simulator should give a warning if a function or a expression return value is not assigned to anything. Using void'() explicitly tells the tool that you wish to ignore the return value and not see the warning.

You can can use other casts too, such as int'(), MyPredefinedStruct'(), 9'(). note that giving a constant in casting will return a bit vector. 9'(4'b0101) == 9'b000_0101

See the IEEE Std 1800-2012 and read section 6.24 for more explanations and examples.