Can I set an enum with its numerical value?

Question

I want to set an enum with the numerical value. Is the following code legal for SystemVerilog?

`define DEC_ADDR   32'hC001CAFE

typedef enum bit [31:0] {
  ILLEGAL_ADDR_0=0,
  DEC_ADDR=`DEC_ADDR
} my_addr_e;

module tb;

initial begin

  my_addr_e addr_name;
  bit [31:0] reg_addr;

  reg_addr = `DEC_ADDR;
  addr_name = reg_addr; // PROBLEM

end

endmodule

Here is the complete code on EDA Playground: http://www.edaplayground.com/s/4/219

Answer 1

Technically speaking, setting an enum with its numerical value is not legal SystemVerilog. SystemVerilog is a strongly typed language, so enums should be set with its named value.

That said, some simulators allow setting enums with numerical values.

The above code can be fixed by adding a static cast:

addr_name = my_addr_e'(reg_addr);