What is the difference between using an initial block vs initializing a reg variable in systemverilog?

Question

What is the difference between the following two examples with regards to simulation?

A)

reg a;
initial a = 1'b0;

and

B)

reg a = 1'b0;

Is it different for logic variables?

Answer 1

The difference is initialization as part of a variable declarations execute before any process started by any initial or always constructs. If you wrote:

bit clk;
initial clk = 1;
always #5 clk++;
always @(posedge clk) ...;

There is a race condition as to whether the @(posedge clk) gets triggered at time 0 or time 10. However with:

bit clk = 1;
always #5 clk++;
always @(posedge clk) ...;

There is no race with the above. The first posedge will come at 10 time units.

Answer 2

The end result is the same, i.e., there won't be any difference from the end user perspective. The difference is that in the first case you are assigning the value during run time, and in the second case you are assigning the value during compile time.