How to fix indentation in Systemverilog source

Question

I am using systemverilog very often.
I am using UltraEdit as text editor. I use also VIM.
Sometimes I have to copy code from some other places and paste it into my code.
It may not be indented properly. It is a difficult task to indent it properly again.

Can anybody suggest any method or tool to do it easily?

Answer 1

Method

1. Visit EDA Playground
2. Paste your code into one of the editor windows
3. Select all text with CTRL-A
4. Reindent all text with SHIFT-TAB

Some backgroud

There is a Verilog mode for Code Mirror which supports SystemVerilog. CodeMirror is an in-browser text editor written in JavaScript which is used on a number of websites, including EDA Playground.

You could also paste and reindent in the example window here, or you could download it yourself and run it locally.