JAL: what is the "alternate link register" x5 for?

Question

The RISC-V specification v2.2 (JAL instruction, page 15) says of the "standard calling convention":

The standard software calling convention uses x1 as the return address register and x5 as an alternate link register.

with the following design comment:

The alternate link register supports calling millicode routines (e.g., those to save and restore registers in compressed code) while preserving the regular return address register.

What is an alternative link register for?

I understand that "link register" is a register to store the pc to jump to on return, and that millicode/microcode are a lower-level instruction format below the ISA level. Is the idea that x5 is used instead of x1 for certain (microcode/millicode) instructions that surround "normal calls" to avoid register shuffling or a spill? Would you have a typical usage example?

It could be helpful to add an explanation of alternate link registers to the Wikipedia article on link registers, which is where I went looking for extra information.

Answer 1

In general millicode instructions shouldn't intersect with normal instructions and an alternative calling convention is needed to call a millicode procedure (from Waterman's PhD Thesis, page 66):

... routines must have an alternate calling convention since the link register must be preserved during their execution. Fortunately, unlike ARM and MIPS, RISC-V’s jump-and-link instruction can write the return address to any integer register, rather than clobbering the ABI-designated link register. Other than that distinction, these millicode routines behave like ordinary procedures

A more specific reason, why the link register should be preserved, is because the millicode is used to implement prologues and epilogues, thus using a regular calling convention will clobber the link register and will defeat the whole idea of using millicode for prologues/epilogues.

Is the idea that x5 is used instead of x1 for certain (microcode/millicode) instructions that surround "normal calls" to avoid register shuffling or a spill?

Yes... to some extent of the word "surround".

Would you have a typical usage example?

See prologue_2, epilogue_2 millicode routines from Waterman's PhD, page 67

00: c919     c.beqz a0, 16
02: 016002ef jal t0, prologue_2
06: 842a     c.mv s0, a0
08: 157d     c.addi a0, -1
0a: ff7ff0ef jal ra, factorial
0e: 02850533 mul a0, a0, s0
12: 0100006f jal x0, epilogue_2
16: 4505     c.li a0, 1
18: 8082     c.jr ra

where prologue_2:

00: 1141 c.addi sp, -16
02: e406 c.sdsp ra, 8(sp)
04: e022 c.sdsp s0, 0(sp)
06: 8282 c.jr t0

and epilogue_2:

00: 60a2 c.ldsp ra, 8(sp)
02: 6402 c.ldsp s0, 0(sp)
04: 0141 c.addi sp, 16
06: 8082 c.jr ra