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I have downloaded the latest...
RISC-V Instruction Set Manual, Volume 1: User-Level ISA
...which is interesting but it never actually gives values for the opcodes/funct3 and other instruction formats. For example, the LOAD/STORE/BRANCH opcodes are listed by name but it does not provide the actual bit values they represent.
Where are all the codes actual listed?
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RISC-V comprises of a base user-level 32-bit integer instruction set. Called RV32I, it includes 47 instructions, which can be grouped into six types: R-type: register-register. I-type: short immediates and loads.
This repo enumerates standard RISC-V instruction opcodes and control and status registers. It also contains a script to convert them into several formats (C, Scala, LaTeX). Artifacts (encoding. h, latex-tables, etc) from this repo are used in other tools and projects like Spike, PK, RISC-V Manual, etc.
The instruction set is designed for a wide range of uses. The base instruction set has a fixed length of 32-bit naturally aligned instructions, and the ISA supports variable length extensions where each instruction can be any number of 16-bit parcels in length.
MUL performs a 32 x 32 register multiply and stores the lower 32 bits of the 64-bit result in a register. MULH and MULHU perform signed and unsigned register multiply, respectively, and store the upper 32 bits of the 64-bit result in a register.
They are also already conveniently encoded in the source code of the sodor project:
https://github.com/ucb-bar/riscv-sodor
for constants that capture the bit patterns in various useful ways, see:
src/common/instructions.scala
or, directly from the browser:
https://github.com/ucb-bar/riscv-sodor/blob/master/src/main/scala/common/instructions.scala
107
https://riscv.org/specifications/
Table 9.1 and all of Chapter 9.
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