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I am currently working on implementing RV32I Base Instruction Set.
I had a question about ADDI instruction. In the manual, how to understand this clause "ADDI rd, rs1, 0 is used to implement the MV rd, rs1 assembler pseudo-instruction."
Does it mean ADDI rd, rs1, 0 is equal to move content of rs1 to register specified by rd?
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RISC-V Assembly Code Remember that addi sign-extends the 12-bit immediate, so a negative immediate will have all 1's in its upper 20 bits. Because all 1's is −1 in two's complement, adding all 1's to the upper immediate results in subtracting 1 from the upper immediate.
RISC-V (pronounced "risk-five" where five refers to the number of generations of RISC architecture that were developed at the University of California, Berkeley since 1981) is an open standard instruction set architecture (ISA) based on established RISC principles.
RISC-V comprises of a base user-level 32-bit integer instruction set. Called RV32I, it includes 47 instructions, which can be grouped into six types: R-type: register-register. I-type: short immediates and loads.
The lw will reload the value that was written by the sw . (Note that the lw in this case may also expand to multiple instructions depending on VAL , whereas the sw is a single instruction regardless of VAL .)
yes ADDI rd, rs1, 0 performs the operation :
rd <- rs1 + 0, that is rd <- rs1
so ADDI rd, rs1, 0 performs MV rd, rs1
It does not performs a move (copy is a better word) of the content of rs1 to the register specified by rd as mentionned in the question. It performs a move (copy again) of the content of rs1 to the register rd.
With an example :
ADDI x3, x5, 0 will copy the content of x5 to x3 - and using the same name as above, in this example : rd is x3 and rs1 is x5.
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The mv x, y (move) pseudo-instruction is just an alias for addi x, y, 0. That means it's syntactic sugar that is implemented inside the assembler.
Since the mv alias is resolved by the assembler mv doesn't have its own opcode and thus isn't a real instruction. Hence it's called a pseudo-instruction.
Using the mv pseudo-instruction arguably describes the purpose of your code more clearly. Certainly, it's slightly less to type and less to parse for a human.
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Yes, ADDI rd, rs1, 0 is the encoding of the MV rd, rs1 instruction.
Many encodings are possible, e.g. XORI rd, rs1, 0 would have the same effect.
The reason for specifying which is the chosen encoding is so a disassembler will output MV rd, rs1 when it sees ADDI rd, rs1, 0, but XORI rd, rs1, 0 will still be disassembled as XORI rd, rs1, 0.
Other instructions have specified encodings, such as NOP being ADDI x0, x0, 0, rather than any of the other instructions which do nothing. Note: register 0 is magic. It always reads as zero, thus writes are lost.
MV instructions set one register's value equal to another register's value, so they would be better described as "copy", as @LiHenyuan wrote.
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