RISC-V: Why set least significant bit to zero in JALR

Question

Why do we need to set the least significant bit to zero in JALR in RISC-V Instruction set as described in the RISC-V Instruction manual?

Is it for alignment propose?

Answer 1

In RISC-V all instructions must be aligned to 4 bytes, but through extensions that allow 16, 48 or 64 bit instructions size, instructions are allowed to be aligned to 2 bytes. As described in the specification (V 2.1, p. 5):

The base RISC-V ISA has fixed-length 32-bit instructions that must be naturally aligned on 32-bit boundaries. However, the standard RISC-V encoding scheme is designed to support ISA extensions with variable-length instructions, where each instruction can be any number of 16-bit instruction parcels in length and parcels are naturally aligned on 16-bit boundaries.

So the least significant bit in the target address of JALR must always be zero. The developers of RISC-V wanted to reuse an existing format instead of making a new one, where the immediate is multiplied by two. As explained on p. 16 in the specification:

Note that the JALR instruction does not treat the 12-bit immediate as multiples of 2 bytes, unlike the conditional branch instructions. This avoids one more immediate format in hardware.

This isn't a real disadvantage, as implementations can you use the least significant bit of the pointers. One example would be to distinguish between function pointers and data pointers, which can be handy for interpreters. Also mentioned in the specification at p. 16:

[...] allows the low bit of function pointers to be used to store auxiliary information.

Answer 2

The smallest instruction in RISC-V is 2 bytes. No valid RISC-V instruction starts at an odd instruction, so there would be no purpose in allowing the least significant bit to be 1.