I have started to work with risc-v few days ago, but yesterday I had a problem. The problem is the following:
I want to compile code for example for the RV32I base integer instruction set and I want to add too the "M" Standard Extension.
When I compile the C code I use the following command
riscv64-unknown-elf-gcc Program.c -o Program.o -m32 -march=RV32IM
Now if for example I want to see assembler code, I use
riscv64-unknown-elf-objdump -d Program.c > Program.dump
Now, if I explore the dump file "Program.dump" . I have noticed that sometimes appear assembly instructions as:
10c6c: 00a12427 fsw fa0,8(sp)
10dd0: 00a42023 sd a0,8(sp)
among many other cases.
If I see the "RISC-V Instruction Set Manual, Volume I: User-Level ISA, Version 2.0" at page 52 I observe that the fsw instruction belongs a RV32F Standard Extension and the sd instruction , it belongs to RV64I.
For this reason, I am confused I don't know if my problem is that I am not compiling well.
My question is: How can I compile C code only for the RV32I base integer instruction and the extension M?
Called RV32I, it includes 47 instructions, which can be grouped into six types: R-type: register-register. I-type: short immediates and loads. S-type: stores.
RISC-V division instruction has both signed and unsigned division and can use either quotient or reminder. If the dividend or divisor is zero, then the divider stalls for two clock cycles; otherwise, it stalls the 33 or 34 clocks depending on the sign, and then “valid out” will be asserted.
zero corresponds to register x0 which always holds the value 0. You can see some instructions are repeated such as LI (Load Immediate) and CALL . The reason is that depending on context these pseudo instructions can result in a variety of different RISC-V instructions.
sb = store byte, sh = store halfword, sw = store word, sd = store doubleword. Adds value of t0 to the value of t1 and stores the sum into a0. Adds value of t0 to the value -10 and stores the sum into a0. Subtracts value of t1 from value of t0 and stores the difference in a0.
As Chris pointed out, the problem seems to be that the libraries have not been built for RV32I.
This is a copy&paste from my instructions here for how to build a pure RV32I toolchain+libraries from git rev 5b1febd
(2015-07-05) of riscv-gnu-toolchain:
sudo mkdir /opt/riscv32i
sudo chown $USER /opt/riscv32i
git clone https://github.com/riscv/riscv-gnu-toolchain riscv-gnu-toolchain-rv32i
cd riscv-gnu-toolchain-rv32i
git checkout 5b1febd
mkdir build; cd build
../configure --with-xlen=32 --with-arch=I --prefix=/opt/riscv32i
make -j$(nproc)
This will install a RV32I toolchain with the riscv32-unknown-elf-
command prefix.
There seems to be a problem with --with-xlen=32 --with-arch=I
in current git head of riscv-gnu-toolchain. I've now reported the issue on github.
If you love us? You can donate to us via Paypal or buy me a coffee so we can maintain and grow! Thank you!
Donate Us With