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In the RISC-V specification, it is written that the immediates in JAL and JALR instructions are converted to jump offsets as :
Sign extend the given immediate to XLEN bits.
Set the LSB to zero.
I have a couple of questions regarding this.
QUESTION 1
For JAL, this gives a range :
000000000000 to 111111111110
that is, 4KiB.
Here, if the LSB is going to have to be zero always, why isn't the immediate just considered as the 12 bits before a mandatory zero LSB for the address, hence increasing the range of addresses to:
[000000000000]0 to [111111111111]0
[ ] represents the given immediate offset, and a zero is added to the end of a given immediate offset internally. That is,
Left shift give address by a bit.
Sign extend the result to XLEN bits.
QUESTION 2
How are positive and negative offsets distinguished from one another? Is the MSB of the given offset used?
1000
What range of addresses can be reached using the RISC-Vjump-and-link(jal) instruction?(In other words, what is the set of possible values for the PC after the jump instruction executes?)injalinstruction, the immediate field has 20 bits.
jal use immediate (20bits) encoding for destination address and can jump +-1MiB range. And save the actual address + 4 in register rd . ( x1 in your example). jalr use indirect address ( x1 in your example) plus a constant of 12bits (0 in your example).
Ultimately the jal can reach -0.5MB to +0.5MB from the jal instruction itself.
The jump-and-link-register instruction ( JALR ) is the union of JAL and JR , meaning that it transfers control to the address in a specified register, and stores the return address in the register file. However, unlike JAL , JALR allows the programmer to specify the destination register of the return address.
JAL has a 20 bit offset and a register as operands.
Its operation is pc := pc + sxt ( imm20 << 1 ).
As you can see by the formula, the branch is pc-relative. The immediate can reach +/- 1 MB from the JAL itself. The immediate is shifted by one bit, the true LSB is always zero, so is not encoded.
Because RISC V supports instructions in multiples of 16-bits (two bytes), we cannot assume the next-to-LSB is also zero, as it would be with MIPS (which has 32-bit instructions).
The register operand in JAL is optionally used to capture the return address in addition to performing the branch.
JAL's function is to perform modestly far pc-relative branches or calls using its 20-bit range. (Contrast with RISC V conditional branch instructions that have only have 12 bits for +/- 4 KB range.)
JALR has a 12 bit offset and two registers as operands.
Its operation is pc := ( rs1 + sxt ( imm12 ) ) & -2.
As you can see by the formula, the branch is register indirect, relative to the value in rs1.
Like JAL, JALR can also capture the the return address.
JALR is used to return from a function (aka RET in assembly. In this form $ra is used as the source register, and no return address is captured). This uses zero for the offset (i.e. an offset is not required).
JALR is also used to perform indirect function calls: calls via function pointer, virtual method dispatches, etc.. These use also use zero for the offset.
JALR can also be used in sequence with AUIPC.
AUIPC has a 20 bit offset and a register as operands.
Its operation is rd := pc + ( imm20 << 12 ).
It computes the upper part of a pc-relative immediate (while also providing a lower part of the pc that is not relative).
Combined with JALR, this can accomplish a 32-bit pc-relative branch or call.
AUIPC r5, labelFarAway # AUIPC encodes upper 20 bits of label's distance from pc
JALR r5, $ra, labelFarAway # JALR encodes the lower 12 bits of same
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