How to typecast integer to unsigned in VHDL

Question

I am trying to divide two integers as following:

variable m0Low : integer := 0;
variable m1Low : integer := 0;
m1Low := divide(m1Low,m0Low);

With the function :

function  divide  (a : UNSIGNED; b : UNSIGNED) return UNSIGNED is    
    variable a1 : unsigned(a'length-1 downto 0):=a;    
    variable b1 : unsigned(b'length-1 downto 0):=b;    
    variable p1 : unsigned(b'length downto 0):= (others => '0');    
    variable i : integer:=0;               
    begin    
        for i in 0 to b'length-1 loop    
            p1(b'length-1 downto 1) := p1(b'length-2 downto 0);    
            p1(0) := a1(a'length-1);    
            a1(a'length-1 downto 1) := a1(a'length-2 downto 0);    
            p1 := p1-b1;    
            if(p1(b'length-1) ='1') then    
                a1(0) :='0';    
                p1 := p1+b1;    
            else    
                a1(0) :='1';    
            end if;
        end loop;    
    return a1;    
end divide;

However, I get the following error: Divide can not have such operands in this context.

I am trying to cast the variables to unsigned m1Low := divide(unsigned(m1Low),unsigned(m0Low));

But I get the following error: The expression can not be converted to type unsigned.

Any idea what I can do? Thanks Haris

Answer 1

To convert integer to unsigned or signed data type over,

use IEEE.NUMERIC_STD.all;

you must use,

to_unsigned(I,U’length);
to_signed(I,S’length)

where I is the integer value and U'length is the unsigned vector length ( the number of bit ).

I didn't verify your code and how it's actually working but my correction on your code is just,

m1Low := to_integer(divide(to_unsigned(m1Low, N),to_unsigned(m0Low, N)));

you should specify N where its the length of your vector depend on your design. I used to_integer() because your function is returning unsigned value to integer variable.

Hope this simple notes help you.