State management in VHDL FSMs

Question

A lot of the FSMs I see in VHDL work by setting a variable "next_state" in the FSM logic and then assign this seperately to the state variable outside of the process.

If there anything wrong with simply writing "state <= state_five;" to set the next state instead? I'm presuming there is a reason that so many people use a separate next state variable instead of directly assigning to the state as I see it all the time, but as far as I can tell there is no difference except that it makes the code longer and more complicated looking.

Have I missed something? Or is it just a question of style? And if so why is that style better, it seems unnecessary to me.

Answer 1

"Is there anything wrong with simply writing state <= state_five;?"

Nothing whatsoever - PROVIDED the state assignment is done in a clocked process.

This leads to the neat simple reliable "single process state machine" style, instead of the unreliable (because it's easy to get the sensitivity lists wrong) two-process style that is taught in WAY too many textbooks and online tutorials.

Search for "single process state machine" and you should be able to find good example material and further discussion.

Historical note : there may have been some synthesis tools in the previous century that had problems with the single-process style; but that's no reason to avoid it now.