VHDL std_logic_vector conversion to signed and unsigned with numeric_std

Question

I have some doubts about the use of the conversions from std_logic_vector to signed/unsigned. I always use the conversion signed(...), unsigned(...), but when I try to use the conversions defined in the library numeric_std (to_signed, to unsigned), it doesn't work. Can someone explain to me why this happens? And why the conversion unsigned() and signed() works?

Answer 1

Because the std_logic_vector and signed/unsigned types are closely related, you can use the typecast way to convert. So signed(a_std_logic_vector) and unsigned(a_std_logic_vector) are okay. However, the functions to convert are also defined in the standard.

Take a look at the VHDL FAQ. This is an old website from the days that newsgroups were still hot, but it still has plenty of good information about VHDL.