VHDL is it valid syntax to use string in Generic?

Question

I have been using Xilinx tools for a while, and they are perfectly fine with code such as the following:

ENTITY Example IS
  GENERIC(
    g_Mode : STRING  := "Normal"); -- "Normal", "Test"
  PORT(
    Clk : IN  STD_LOGIC;
    -- ETC 
    );

END Example;

ARCHITECTURE rtl OF Example IS

Normal_g : IF g_Mode = "Normal" GENERATE
  -- Normal Operation Code Here
END GENERATE Normal_g;

Test_g : IF g_Mode = "Test" GENERATE
  -- Test Operation Code Here
END GENERATE Test_g;

However I have recently switched to using Lattice Tools and I get an error the second time I check the g_Mode. The error is, "Comparison between unequal length arrays always returns FALSE". So it seems like one of the two generate statements will never execute. My question is, is this legal VHDL syntax and therefore a problem with the Lattice Tools? Or should my code style change to not use strings as Generics?

Answer 1

Using a string for a generic is legal. However look at the actual error message : it is perfectly clear.

One solution would be to make all the strings the same length. Test_g : IF g_Mode = "Testxx" GENERATE should compile and work as expected.

A better solution - since a string comparison adds no real value here - might be to declare an enumeration type type Mode is (Normal, Test, Special); in a package, and make your generic of type Mode. (This also avoids accidents with mis-spellings for example)

Or if there will only ever be two modes, make the generic a boolean called Testing. Then the normal case becomes if not Testing generate...