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What's the difference between $stop and $finish in Verilog?

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verilog

People also ask

What does $finish do in Verilog?

$finish is a Verilog system task that tells the simulator to terminate the current simulation. If the last block had a delay of 30 time units like shown below, the simulation would have ended at 30 time units thereby killing all the other initial blocks that are active at that time.

What is the difference between $display and $monitor and $write and $strobe?

$display and $write prints the text when the statement is executed during simulation. The only difference between the two is that $display writes out a newline character at the end of the text, whereas $write does not. $strobe prints the text when all simulation events in the current time step have executed.

What is the difference between wire and reg data type?

The wire is used for a continuous assignment whereas reg is used in a procedural assignment.

Can we use always block in testbench?

In the testbenches, the 'always' statement can be written with or without the sensitivity list as shown in Listing 9.3. Unlike 'initial' block, the 'always' block executes forever (if not terminated using 'stop' keyword).

$finish exits the simulation and gives control back to the operating system.

$stop suspends the simulation and puts a simulator in an interactive mode.


According to the IEEE Standard for Verilog (1364-2005, Section 17.4, "Simulation control system tasks"), $stop should suspend the simulation, and $finish should make the simulator exit and pass control back to the host operating system. Of course, different simulators may implement the specification in subtly different ways, and not all simulators are 100% compliant with the spec.

The documentation for your simulator might provide a more detailed description of its behavior, especially with respect to GUI vs. command-line modes.


A quick reference link:

$finish;
    Finishes a simulation and exits the simulation process.
$stop;
    Halts a simulation and enters an interactive debug mode.

$stop : Undesired termination of the simulation. All the system activities are suspended. $finish : Used to relieve the compiler.

Good analogy would be $finish is like shutting down your computer and $stop is like abruptly pulling its plug.

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