$size, $bits, verilog

Question

What is the difference between $size and $bits operator in verilog.? if I've variables, [9:0]a,[6:0]b,[31:0]c.

c <= [($size(a)+$size(b)-1]-:$bits(b)];

What will be the output at 'c' from the above expression?

Answer 1

$size() gives the number of bits for a single dimension. $bits() gives the number of bits to completely represent the variable.

For example:

reg [9:0] a;
reg [9:0] b [5:0];

initial begin
  $display("a Size ", $size(a));
  $display("a Bits ", $bits(a));
  $display("b Size ", $size(b));
  $display("b Bits ", $bits(b)) ;
end

Gives :

a Size          10
a Bits          10
b Size           6 // Depth of memory
b Bits          60 // Width * Depth

In your case you just have 1 dimensional arrays, not memories or structs so $size() and $bits() would be the same thing.