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New posts in cpu-architecture
.csproj's platform specific ItemGroup works for assembly references but not content includes?
Oct 21, 2021
.net
assemblies
cpu-architecture
How are interrupts handled by dual processor machines?
Oct 09, 2019
hardware
cpu
multicore
interrupt
cpu-architecture
Cache bandwidth per tick for modern CPUs
Sep 14, 2022
performance
caching
cpu
cpu-architecture
cpu-cache
How can ARM's MOV instruction work with a large number as the second operand?
Sep 13, 2022
assembly
arm
cpu-architecture
machine-code
immediate-operand
Are all programs eventually converted to assembly instructions?
Oct 04, 2022
assembly
compilation
cpu-architecture
Why are there only four registers?
Jul 27, 2018
x86
cpu-architecture
How many bits is a WORD and is that constant over different architectures?
Nov 10, 2022
data-structures
assembly
naming
cpu-architecture
Setup targeting both x86 and x64?
Sep 16, 2022
c#
installation
cpu-architecture
Does lock xchg have the same behavior as mfence?
Feb 19, 2022
multithreading
assembly
x86
cpu-architecture
memory-barriers
intel
How to deal with linker error : error-cannot find -lgcc
Oct 14, 2022
c
linux
gcc
makefile
cpu-architecture
Haswell memory access
Sep 12, 2022
performance
x86
cpu-architecture
avx2
intel-pmu
difference between speculation and prediction
Mar 08, 2022
cpu-architecture
prediction
speculative-execution
Why did Intel change the static branch prediction mechanism over these years?
Oct 01, 2022
x86
compiler-construction
intel
cpu-architecture
branch-prediction
Why are C++ int and long types both 4 bytes?
Sep 11, 2022
c++
cpu-architecture
Branch target prediction in conjunction with branch prediction?
Sep 06, 2022
x86
cpu-architecture
branch-prediction
Does a thread waiting on IO also block a core?
Sep 06, 2022
multithreading
asynchronous
blocking
synchronous
cpu-architecture
TLB misses vs cache misses?
Sep 06, 2022
performance
caching
operating-system
cpu-architecture
tlb
What is the purpose of the Parity Flag on a CPU?
Sep 06, 2022
assembly
cpu-architecture
parity
eflags
When an interrupt occurs, what happens to instructions in the pipeline?
Sep 14, 2022
interrupt
cpu-architecture
why are separate icache and dcache needed [duplicate]
Sep 05, 2022
caching
x86
cpu-architecture
cpu-cache
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