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Are there SIMD(SSE / AVX) instructions in the x86-compatible accelerators MIC Intel Xeon Phi?
http://en.wikipedia.org/wiki/Xeon_Phi
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These processors succeed the Intel Xeon processor v4 family based on the Broadwell (BDW) microarchitecture, which supports instructions from MMX and SSE to AVX and AVX2.
SSE and AVX have 16 registers each. On SSE they are referenced as XMM0-XMM15, and on AVX they are called YMM0-YMM15. XMM registers are 128 bits long, whereas YMM are 256bit. SSE adds three typedefs: __m128 , __m128d and __m128i .
The only difference between AVX and AVX2 for floating point code is availability of new FMA instruction – both AVX and AVX2 have 256-bit FP registers. The main advantage of new ISA of AVX2 is for integer code/data types – there you can expect up to 2x speedup, but 8% for FP code is good speedup of AVX2 over AVX.
Yes, current generation of Intel Xeon Phi co-processors (codename "Knight's Corner", abbreviated KNC) supports 512-bit SIMD instruction set called "Intel® Initial Many Core Instructions" (abbreviated Intel® IMCI).
Intel IMCI is not "compatible with" and is not equialent to SSE, AVX, AVX2 or AVX-512 ISA. However it's officially announced that next planned generations of Xeon Phi (codename "Knight's Landing", abbreviated KNL) will support AVX-512 ISA.
Both Intel IMCI (supported by KNC) and AVX-512 (to be supported by KNL) are 512-bit SIMD instruction sets, supporting FMA and allowing to pack 8 double precision or 16 single precision floating-point numbers, or 16 32-bit integers (i.e. two times "more" than AVX or AVX2).
While KNC is unable to "run" SSE or AVX binaries, it often doesn't matter, because in order to generate your application binary to be able to run on KNC - you need to recompile your code using Intel C/C++/Fortran Compiler, which is known to automatically or semi-automatically generate relatively efficient vector codes (for SSE, AVX, IMCI, etc) and also gives you capability to use IMCI intrinsics if needed.
Side note: for Knights Landing (with AVX-512 support) Intel toolchain will not be a sole option anymore, but it will likely continue to provide many advantages, including solid explicit- and auto- vectorier as well as good level of integration with Intel profiling tools (note for example AVX-512 analysis in Intel (Vectorization) Advisor) .
AVX-512 ISA is compatible with SSE, AVX and AVX2. Therefore applications compiled for AVX on Xeon will run on KNL, while applications compiled for AVX-512 on Xeon Phi KNL will normally run on future generations of Xeon (to support AVX-512 in future).
The difference between AVX, IMCI and future AVX-512 instruction sets could easily be explored using following online guide: http://software.intel.com/sites/landingpage/IntrinsicsGuide/
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