In the Intel 64 and IA-32 Architectures Software Developer's Manual, Row F table A-4 Appendix A.3 Volume 2C (Order Number 326018-045US January 2013) is unique in that it has a prefix sub-row for a combination of two prefixes: 0x66 and 0xF2.
The only opcode for which this is relevant is 0x0F38F1 (CRC32). For the prefix 0xF2 alone, the source operand is Ey (memory or general purpose register; 32 bit or 64 bit), and for the prefixes 0x66 and 0xF2 together, the source operand is Ew (memory or general purpose register; always 16 bit)
But these source operands are identical to what they would be if 0x66 were simply the optional operand size override prefix instead of the first of a combination of two mandatory prefixes. In fact, 0x66 as an optional prefix is how the CRC32 instruction is documented (implicitly: identical byte sequences for both 16 bit and 32 bit source operands) in Chapter 3.2 Volume 2A. It seems that the table could have omitted the 0x66 and 0xF2 row and documented the source operand as Ev (memory or general purpose register; 16 bit or 32 bit or 64 bit) in the 0xF2 row.
Is there a reason why the opcode map documents the source operand for opcode 0x0F38F1 in this unique way?
EDIT: Added version of manual
This opcode is shared with the Atom's MOVBE
instruction. I think this is how it looks for all combinations:
0F 38 F1 movbe My, Gy
66 0F 38 F1 movbe Mw, Gw
66 F2 0F 38 F1 crc32 Gd, Ew
F2 0F 38 F1 crc32 Gd, Ey
F2 66 0F 38 F1 crc32 Gd, Ew
EDIT: for most of opcodes in the 0F38 and 0F3A groups, the 66 prefix is a mandatory prefix which defines the actual instruction, and not the usual operand-size prefix:
Three-byte opcodes that are 4 bytes in length begin with a mandatory prefix (66H, F2H, or F3H) and two escape bytes (0F38H or 0F3AH). The upper and lower four bits of the fourth byte are used to index a particular row and column in Table A-4 or Table A-5.
That's why the case of the additional, optional 66 prefix used in its traditional role of operand-size override has to be listed separately.
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