Menu
According to "Computer Architecture and Organization" by Miles Murdoca and Vincent Heuring,
CISC instructions do not fit pipelined architectures very well. For pipelining to work effectively, each instruction needs to have similarities to other instructions, at least in terms of relative instruction complexity.
Why is this true? What is meant by an instruction's complexity; don't all instructions take one clock cycle to begin execution? If the instruction is reading or writing to memory then it would take longer but RISC processors read or write to memory too (of course)?
803
In CISC, there are often mixes of simpler instructions, and more complicated instructions that take longer. So in a pipeline there are things called hazards that can create problems for smooth pipelining. X86 Floating Point instructions would be longer than x86 load or store, for example.
Because RISC instructions are simpler than those used in pre-RISC processors (now called CISC, or Complex Instruction Set Computer), they are more conducive to pipelining. While CISC instructions varied in length, RISC instructions are all the same length and can be fetched in a single operation.
Characteristic of CISC – Complex instruction, hence complex instruction decoding. Instructions are larger than one-word size. Instruction may take more than a single clock cycle to get executed. Less number of general-purpose registers as operations get performed in memory itself.
CISC ISAs use more transistors in the hardware to implement more instructions and more complex instructions as well. RISC needs more RAM, whereas CISC has an emphasis on smaller code size and uses less RAM overall than RISC.
The "complexity" of the instructions is related to how much their size and format can vary. Take x86 IA32 (Intel 32-bits) architecture for instance, which is CISC. The size of instructions can range from 1 to 15 bytes, and their format varies a lot too (the format being how many bits are used for each field, where those bits are located and so on).
This means that you'll only know when you are done fetching the instruction once you start decoding it. Some instructions will take only a cycle to be fetched, others more, and this complicates the pipeline process.
All ARM instructions (RISC architecture), on the other hand, have exactly 4 bytes. So once you fetch 4 bytes you know that you can send those bytes for the decoding phase of the pipeline and you can immediately start fetching the next instruction.
50
If you love us? You can donate to us via Paypal or buy me a coffee so we can maintain and grow! Thank you!
Donate Us With
