What is practical application of x86 RCL/RCR instructions?

Question

I'm interested in practical applications, even if they are outdated by modern standards.

There's similar question, about ROL and ROR here, but it doesn't really answer about RCL/RCR.

I can come up with some applications for RCL, RCR with operand 1 (i.e. for some LFSRs), but i can't think of any sensible application with non 1 operand.

So can anyone enlighten me?

P.S. sample code is more than welcomed.

update 1: as Peter Cordes mentioned in comments below, one (quite obvious) application is shrd/shld. (IIRC rcl/rcr instructions were already in 8080)

Maybe 'non 1' above was not clear, but mind that I'm mostly interested in usage, where operand is != 1 (RC(L|R) REG, c with c being either > 1 or == cl).

Answer 1

In shifting operations, these instructions have the same role as the the add-with-carry (adc) or subtract-with-carry (sbb) instructions in additions:

It is used as second instruction when processing numbers that are longer than the maximum size of a CPU register so the number must be processed using multiple operations.

Example: On a 386 CPU you can perform 32-bit operations using a single instruction. However, you might want to process 320-bit integer numbers.

Let's say we have a 4-bit CPU and we want to perform a "arithmetic right shift" (sar) operation on a 16-bit integer number:

Integer: ABCDEFGHIJKLMNOP  (A-P = some bits that may be 1 or 0)

Operation on a 16 bit CPU:

    ABCDEFGHIJKLMNOP (SAR 1) -> AABCDEFGHIJKLMNO, CF = P

Operation on a 4 bit CPU:

    ABCD (SAR 1) -> AABC, CF = D
    EFGH, CF = D (RCR 1) -> DEFG, CF = H
    IJKL, CF = H (RCR 1) -> HIJK, CF = L
    MNOP, CF = L (RCR 1) -> LMNO, CF = P

So the final result on the 4-bit CPU is AABCDEFGHIJKLMNO, CF = P

Of course the same example would work with a 256-bit number on a 64-bit CPU...

Please also note:

Using add/adc, sub/sbc or shl/rcl we start at the low bits and continue with the high bits. However, using shr/rcr or sar/rcr it is the other way round.