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When you declare something as input or output, how do you know if you have to also declare it as a reg or a wire?
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So, outputs can be either reg or wire, but an input cannot be a reg. So, in your example you could declare an internal - temporary variable as reg and an input signal as wire.
wire elements must be continuously driven by something, and cannot store a value. Henceforth, they are assigned values using continuous assignment statements. reg can be used to create registers in procedural blocks. Thus, it can store some value.
As you can see from the example above, a wire can be assigned a value by an assign statement. Default data type is wire: this means that if you declare a variable without specifying reg or wire, it will be a 1-bit wide wire. Now, coming to reg data type, reg can store value and drive strength.
There is no difference between reg and logic other than their spelling. The keyword reg remains because SystemVerilog is %100 percent backward compatible with Verilog.
reg and wire specify how the object will be assigned and are therefore only meaningful for outputs.
If you plan to assign your output in sequential code,such as within an always block, declare it as a reg (which really is a misnomer for "variable" in Verilog). Otherwise, it should be a wire, which is also the default.
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