What do curly braces mean in Verilog?

Question

I am having a hard time understanding the following syntax in Verilog:

input  [15:0] a;      // 16-bit input output [31:0] result; // 32-bit output assign result = {{16{a[15]}}, {a[15:0]}}; 

I know the assign statement will wire something up to the result bus using wires and combinational logic, but what's up with the curly braces and 16{a[15]}?

Answer 1

The curly braces mean concatenation, from most significant bit (MSB) on the left down to the least significant bit (LSB) on the right. You are creating a 32-bit bus (result) whose 16 most significant bits consist of 16 copies of bit 15 (the MSB) of the a bus, and whose 16 least significant bits consist of just the a bus (this particular construction is known as sign extension, which is needed e.g. to right-shift a negative number in two's complement form and keep it negative rather than introduce zeros into the MSBits).

For what it's worth, the nested curly braces around a[15:0] are superfluous.

Answer 2

As Matt said, the curly braces are for concatenation. The extra curly braces around 16{a[15]} are the replication operator. They are described in the IEEE Standard for Verilog document (Std 1364-2005), section "5.1.14 Concatenations".

{16{a[15]}} 

is the same as

{     a[15], a[15], a[15], a[15], a[15], a[15], a[15], a[15],    a[15], a[15], a[15], a[15], a[15], a[15], a[15], a[15] } 

In bit-blasted form,

assign result = {{16{a[15]}}, {a[15:0]}}; 

is the same as:

assign result[ 0] = a[ 0]; assign result[ 1] = a[ 1]; assign result[ 2] = a[ 2]; assign result[ 3] = a[ 3]; assign result[ 4] = a[ 4]; assign result[ 5] = a[ 5]; assign result[ 6] = a[ 6]; assign result[ 7] = a[ 7]; assign result[ 8] = a[ 8]; assign result[ 9] = a[ 9]; assign result[10] = a[10]; assign result[11] = a[11]; assign result[12] = a[12]; assign result[13] = a[13]; assign result[14] = a[14]; assign result[15] = a[15]; assign result[16] = a[15]; assign result[17] = a[15]; assign result[18] = a[15]; assign result[19] = a[15]; assign result[20] = a[15]; assign result[21] = a[15]; assign result[22] = a[15]; assign result[23] = a[15]; assign result[24] = a[15]; assign result[25] = a[15]; assign result[26] = a[15]; assign result[27] = a[15]; assign result[28] = a[15]; assign result[29] = a[15]; assign result[30] = a[15]; assign result[31] = a[15];