Unable to disable Hardware prefetcher in Core i7

Question

I am getting Error while trying to disable Hardware prefetcher in my Core i7 system. I am following the method as per the link How do I programmatically disable hardware prefetching?

In my system

grep -i msr /boot/config-$(uname -r)

CONFIG_X86_DEBUGCTLMSR=y

CONFIG_X86_MSR=y

CONFIG_SCSI_ARCMSR=m

Here is my error message

root@ ./rdmsr 0x1a0

850089

[root@ ./wrmsr -p 0 0x1a0 0x850289 (to disable hardware prefetcher in Core i7)

wrmsr:pwrite: Input/output error

I am getting same error for disabling Adjacent cache line prefetcher

Any idea how to resolve this problem ? Thanks in advance .

Answer 1

MSR specifications are specific to Intel processor families as described in chapter 35 of the Intel Architectures Software Developer Manuals As consequence, you have to check first that you can disable through MSRs the prefetcher for your CPU and then check which bits of which register must be toggled for that.

For my processor, Intel Xeon 5650 (06_2CH family) the manual specifies the bits 10 to 8 of the register IA32_MISC_ENABLE at address 0x1A0 are reserved. I guess that this means I can't toggle prefetcher on and off through MSR. According to an answer from an Intel employee here: "Intel has not disclosed how to disable the prefetchers on processors from Nehalem onward. You'll need to disable the prefetchers using options in the BIOS."

On my workstation, running

sudo wrmsr -p 0 0x1a0 0x850289

results in:

wrmsr: CPU 0 cannot set MSR 0x000001a0 to 0x0000000000850289

but

sudo wrmsr -p 0 0x1a0 0x850088

works.

This seems to confirm that I can't disable prefetching using MSRs. Note that this error is defferent from yours, and after reading the Intel manual mentioned above chapter 35.9 it also seems that for your processor you can't disbale the prefetcher with MSRs.I dont know why we don't have the same error message, what is your version of the msr module and Linux kernel ? (modinfo msr)

As a consequence the BIOS maybe the only way to disable the different prefetchers, it's the case for my Xeon 5650.

Answer 2

It turns out 0x1A0 bits 9 and 19 is the right MSR/bits for Pentium 4 and some other older models, but 0x1A4 bits 0-3 are the right MSR bits for the several recent models from Nehalem onwards. I tested 0x1A4 with a Skylake server and it worked as well, whereas 0x1A0 did not.

Quick documentation here: Disclosure of H/W prefetcher control on some Intel processors

There is more complete documentation about this and other MSRs on vol3 of the developer's manual: (click here). The document also confirms that 0x1A0 bits 9 and 19 were used for this in older processor models but 0x14A is used for more recent models.

The other MSR's look fairly interesting for experimenting too ('disable L3 cache' anyone?). Just make sure to look for the MSRs under the right processor family!