test bench for writing verilog output to a text file

Question

i am unable to get correct output in a text file however simulation in modelsim is quite ok.. but while writing it to text file im getting XX for every input. may be there is some syntax error or some other. if any can help plz write down test bench for writing dout (output )of a flipflop (as an example) with every dout(output) showing in a new line in a text file.

Code:

module LFSR( clk,reset,out);
parameter width =4;
input clk,reset;
output [width-1:0] out ;
reg [width-1:0] lfsr;

integer r;
wire feedback = lfsr[width-1]^lfsr[width-2];


always @(posedge clk)
  if (reset)
    begin
      lfsr <= 4'b1000; 
    end
  else
    begin
      lfsr[0] <= feedback;
      for(r=1;r<width;r=r+1)
        lfsr[r]<=lfsr[r-1];
    end

  assign out=lfsr;
endmodule

Testbench:

module aaatest();

  parameter width =4;
  reg clk,reset;
  wire [width-1:0] out;
  reg [width-1:0] lfsr[13:0];
  integer f,i;

  initial
    begin
      f = $fopen("output.txt","w");
    end

    LFSR patt (clk,reset,out);

    always #5 clk=~clk;

    initial begin
      clk=1; reset=1;
      #10 reset=0;
      # 140 $stop;
    end

    initial
      begin
        clk=1;
        for (i = 0; i<14; i=i+1)
          @(posedge clk)
            lfsr[i]<= out;
      end

    initial begin
      for (i = 0; i<14; i=i+1)
        $fwrite(f,"%b\n",lfsr[i]);
    end

    initial begin
      $display("clk out");
      $monitor("%b,%b", clk, out);
    end   

    initial
      begin
        $fclose(f);  
      end
    endmodule

Answer 1

I would like you to think about these sections of code:

initial begin
  f = $fopen("output.txt","w");
end

initial begin
  for (i = 0; i<14; i=i+1)
    $fwrite(f,"%b\n",lfsr[i]);
end

initial begin
  $fclose(f);  
end

When describing hardware we have a massively parallel simulation. All initials are meant to start at the same time, time 0.

If this works at all, as there is no guarantee that the file will be opened before you write to it, you are writing the file at time zero before you have even reset the logic your simulating.

Something like below might be more appropriate:

initial begin
  f = $fopen("output.txt","w");

  @(negedge reset); //Wait for reset to be released
  @(posedge clk);   //Wait for fisrt clock out of reset

  for (i = 0; i<14; i=i+1) begin
    $fwrite(f,"%b\n",lfsr[i]);
  end

  $fclose(f);  
end

To follow up on Gregs suggestions the reset being released too early consider something similar to:

initial begin
  clk=0; reset=1; //Clock low at time zero
  @(posedge clk);
  @(posedge clk);
  reset=0;
  # 140 $stop;
end

Which keep reset asserted for 2 clock rising edges.

Update with working example

There are a few odd things happening, you call $stop (Not $finish) after #140 but also try to loop 14 times, the $stop means only 4 loops are executed.

Your test program is made up of 2 initial begins working in parallel rather than one program that is sequentially executed. You had no delay in writing out your text file and you wrote the buffered version of the lfsr rather than the lfsr output directly.

The following example simulates correctly and writes the text file your looking for:

module aaatest();

  parameter width =4;
  reg   clk,reset;
  wire [width-1:0] out;
  reg  [width-1:0] lfsr[13:0];
  integer f,i;

  LFSR patt (clk,reset,out);

  always #5 clk=~clk;

  //Clock and reset release
  initial begin
    clk=0; reset=1; //Clock low at time zero
    @(posedge clk);
    @(posedge clk);
    reset=0;
  end

  initial begin
    f = $fopen("output.txt","w");

    @(negedge reset); //Wait for reset to be released
    @(posedge clk);   //Wait for fisrt clock out of reset

    for (i = 0; i<14; i=i+1) begin
      @(posedge clk);
      lfsr[i] <= out;
      $display("LFSR %b", out);
      $fwrite(f,"%b\n",   out);
    end

    $fclose(f);  

    $finish;
  end
endmodule