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New posts in intel-pmu

Why are the user-mode L1 store miss events only counted when there is a store initialization loop?

x86 intel performancecounter cpu-cache intel-pmu

Hardware cache events and perf

linux performance x86 perf intel-pmu

rdpmc: surprising behavior

performance assembly x86 performancecounter intel-pmu

Can the LSD issue uOPs from the next iteration of the detected loop?

assembly x86 cpu-architecture intel-pmu

Why does the number of uops per iteration increase with the stride of streaming loads?

assembly x86 cpu-architecture intel-pmu

Reliability of Xcode Instrument's disassembly time profiling

xcode x86 profiling instruments intel-pmu

What is the overhead of using Intel Last Branch Record?

x86 intel trace branch-prediction intel-pmu

Can the Intel performance monitor counters be used to measure memory bandwidth?

performance x86 intel-pmu memory-bandwidth

Haswell memory access

performance x86 cpu-architecture avx2 intel-pmu
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