Explicitly define how LUTs and slices are used in Xilinx XST tool?

Question

I'm trying to implement some very specific behavior of LUTs and slices, written in VHDL for Xilinx Virtex 5 FPGA synthesized using XST tool(s). I don't know if I can achieve my behavior by having the tools infer what I mean, so how do I explicitly direct this to happen?

I'm talking about use of the 6-input LUTs on Virtex5, of which there are 4 of them in a CLB.

I want to explicitly state: - Inputs to each of the 4 LUTs within ONE CLB slice - Route the 'S' outputs from the 4 XORCYs - Specify INPUT of the 'first' MUXCY (C0) - Route OUTPUT of the '4th' MUXCY (Cn) - Be able to specify the inputs of each LUT of the CLB in a specific order, since they obviously cascade..

Ideally I'd love to just instantiate a 'CLB' in VHDL with all inputs and outputs, and be able to map these..

I researched the documentation pretty heavily and haven't found anything really

Answer 1

Saar suggests you use LUT6 to explicitly instantiate a LUT. I prefer to control technology mapping with a LUT_MAP constraint. It requires less maintenance and your HDL code remains device agnostic and simulator friendly.

Here is an example.

(* LUT_MAP="yes" *)
module mux4(sel, a, b, c, d, o);
input [1:0] sel;
input       a;
input       b;
input       c;
input       d;
output reg  o;

always @* begin
    case(sel)
    2'b00: o <= a;
    2'b01: o <= b;
    2'b10: o <= c;
    2'b11: o <= d;
    endcase
end
endmodule

This lets you write arbitrary combinational logic and tell synthesis (XST) that this (up to 6-input, one output) module must be implemented in a single LUT. If you combine that with KEEP_HIERARCHY and RLOC constraints you can build up RPMs (relationally placed macros).

(* KEEP_HIERARCHY="true" *)
module mux4x4p4(sel, a, b, c, d, o);
input  [1:0] sel;
input  [3:0] a;
input  [3:0] b;
input  [3:0] c;
input  [3:0] d;
output [3:0] o;

(* RLOC="X0Y0" *)
mux4 m0(sel, a[0], b[0], c[0], d[0], o[0]);
(* RLOC="X0Y0" *)
mux4 m1(sel, a[1], b[1], c[1], d[1], o[1]);
(* RLOC="X0Y0" *)
mux4 m2(sel, a[2], b[2], c[2], d[2], o[2]);
(* RLOC="X0Y0" *)
mux4 m3(sel, a[3], b[3], c[3], d[3], o[3]);
endmodule

There is more information on RPMs for datapaths on my old web site, www.fpgacpu.org. For example, The Art of High Performance FPGA Design: http://www.fpgacpu.org/log/aug02.html#art

Happy hacking!

Answer 2

You might be able to achieve the desired behaviour using RLOC and BEL constraints. You can embed the constraints in the VHDL:

VHDL Syntax

Declare the VHDL constraint as follows:
attribute bel : string;

Specify the VHDL constraint as follows:
attribute bel of {component_name| label_name}: {component|label} is {F|G|FFA|FFB|FFC|FFD|FFX|FFY|XORF|XORG|A6LUT|B6LUT|C6LUT|D6LUT|A5LUT|B5LUT|C5LUT|D5LUT}";

Look in the Xilinx Constraints Guide for more details.

See also this post on comp.arch.fpga for some example VHDL: http://newsgroups.derkeiler.com/Archive/Comp/comp.arch.fpga/2008-05/msg00560.html