VHDL synthesis of if statements without elsif and else condition

Question

I am trying to understand better how synthesis works for a process like this one where no else conditions is specified.

I assume this is not the way to code because I am not considering other options but my question is how is going this code to be interpreted?

process(clock)
begin
if (clock'event and clock ='1') then 
  if sel0 = '1' then qout <= A - B;    end if; 
  if sel1 = '1' then qout <=  qout sra 2;        end if;
end if;
end process; 

IF statements are going to be synthesized into multiplexers. I think that for this example both the multiplexers are going to be connected together in a chain with a D register at the end for the registered value of out. I am guessing what is the value of qout when sel0 '0' and sel1 '0'? What happens to each multiplexer when its selector is '0'? Is the network keeping the same output, inferring a latch?

Thanks.

Answer 1

To show and learn how the synthesis tools implements the design, you can for example synthesize with Altera Quartus II and then use the build-in RTL viewer to show the high level representation of the resulting design.

The code, using 1 bit vectors to simplify the structure, gives the result shown below.

So this shows a flip-flop that is updated every cycle, with value:

• qout_sra_2 if sel1 = '1'
• a_minus_b if sel1 = '0' and sel0 = '1'
• qout (reassign with same value) if sel1 = '0' and sel0 = '0'

Thus equivalent with:

if clock'event and clock ='1' then 
  if sel1 = '1' then
    qout <= qout sra 2;
  elsif sel0 = '1' then
    qout <= A - B;
  else
    qout <= qout;
  end if; 
end if;

Other synthesis tools may implement it in a different, like Xilinx ISE that uses clock enable on the flip-flop, thus giving the result below.

So this shows a flip-flop that is updated if either sel0 or sel1 is '1', with value:

• qout_sra_2 if sel1 = '1'
• a_minus_b if sel1 = '0'

Thus equivalent with:

if clock'event and clock ='1' then 
  if not ((sel0 = '0') and (sel1 = '0')) then  -- (sel0 = '1') or (sel1 = '1')
    if sel1 = '1' then
      qout <= qout sra 2;
    else
      qout <= A - B;
    end if;
  end if;
end if; 

Answer 2

You will basically get a mux and a register (in addition to the logic that handles the calculation for each input, of course). There is no need for a latch, because the register will be clock enabled, so the input network can be purely combinational.

There is also no need for 2 muxes. Because of the way signal assignment works in VHDL, the following code segment:

if sel0 = '1' then
  qout <= A - B;
end if; 
if sel1 = '1' then
  qout <= qout sra 2;
end if;

is equivalent to:

if sel1 = '1' then
  qout <= qout sra 2;
elsif sel0 = '1' then
  qout <= A - B;
end if; 

The later assignment overrides the earlier one if both if conditions are true. Implied after that is "else do nothing", i.e. "else do not clock enable the register". The logic can be reduced to a mux that depends only on sel1 (if sel1 is '0', the output of the network is either what would be selected by sel0, or a don't-care, since it won't be clocked in). The clock enable for the register would be sel0 or sel1. That's how I'd do it, at least.