Defining interface inside a package

Question

In IEEE Std 1800-2012 we can find description of packages and such information:

Types, nets, variables, tasks, functions, sequences, properties, and checkers may be declared within a package

I was wondering, if there is any particular reason why interfaces can't be defined inside a package? It seems to me that it might be useful, but apparently the creators of the standard wouldn't agree.

Answer 1

The main reason has to do with the different namespaces that exist in SystemVerilog, and requirements for separate compilation. Interfaces are one kind of design element (See the 1800-2012 LRM section 3.2 Design elements) whose definitions exist in their own namespace and do not require compilation before use. Packages were intended for types that have a specific compilation order requirement as well as create a separate namespace. Over the different revisions of the standard, that original intent may have been lost.

Verilog has a configuration mechanism that allows you to have different implementations of the same design elements existing in different libraries.