Why did RV64 introduce new opcodes for 32-bit operations instead of the 64-bit ones

Question

While going through the RISC-V Specification I've noticed that the 64-bit version differs from the 32-bit one in the fact, that it

1. Widened the registers to 64-bit
2. Changed the instructions to act on the whole 64-bit range.
3. Added new instruction to perform 32-bit operations

This makes RV32 code incompatible to RV64. However if the 64-bit version had been implemented by:

1. Widening the registers to 64-bit
2. Renaming ADD/SUB/SHL/.. to ADDW/SUBW/SHLW/.. and keep them operating only on 32-bit with sign extend.
3. Add new instructions ADD/SUB/SHL/.. or ADDD/SUBD/SHLD/.. to act on the full 64-bit

This would have allowed RV32 programs to run on RV64 as well. For implementing the CPU the effort would remain the same since in both cases the 64-bit and the 32-bit instructions would have to be implemented and only the opcodes for the 64-bit and the 32-bit versions would have been swapped in contrast to the specification. (Except maybe for the multiply instruction.)

So why did RISC-V decided to assign new opcodes to the 32-bit operations instead of to the 64-bit operations in RV64?

Answer 1

The RV64 and RV32 are quite compatible. If the program don’t rely on implicit modulo 32-bit arithmetic and all addresses fit into 32-bit, the machine code could be the same. However it is very easy to add complete RV32 user mode to RV64 processor.

The 64-bit superset of RV32 would be too complicated. There are not enough opcode space for AUIPC, JAL, LOAD, STORE and BRANCH. It is worse with additional extensions.

The few 32-bit instructions in RV64 are mostly for programs overusing modulo 32-bit arithmetic. This is very common problem. The fast and portable code should avoid them, though.