What is a processor hint?

Question

In the context of the Intel® 64 and IA-32 Architectures Software Developer Manuals, what exactly is a processor "hint?"

I see it in a few sections:

1. In the description of PREFETCHWT1 -Prefetch hint T1 with intent to write.

2. In the SSE4 introduction "The technology also provides a hint that can improve memory throughput when reading from uncacheable WC memory type." Which led to me to this answer regarding WC memory but no clear description of what a hint is.

3. Next I read one of the SSE4 instructions can perform a load with a "streaming" hint. This led me to the SSE4 Programming reference where I discovered hints can be temporal or non-temporal.

4. The streaming load hint instruction itself MOVNTDQA "provides a non-temporal hint"

5. Further into the manual, I find Transactional Synchronization Extensions(TSX) use a "prefix hint" in XACQUIRE and XRELEASE

6. In the AVX 512 bit section when describing VGATHERPF0DPD and others (there are 7 more of these types of instructions all with the /PS option). In these situations we have either a T0 or T1 hint using dword or qword indices.

7. The most insightful time I saw hint used in the manual (this list is in order) came in section 10.4.6.1 where it reads

"The non-temporal hint directs the processor to store the data to memory without writing the data into the cache hierarchy."

This is in the 'Cacheability Control Instructions' section involving MOVNTQ, MOVNTPS, MASKMOVQ so would a temporal hint write to a cache line? I'm inferring this as if it's the opposite of a non-temporal hint?

Other links I used in an attempt to piece together the meaning of processor hints:

• Stack Overflow answer to what the opposite of a hint is.
• this answer using a FreeBSD manpage.

The Wikipedia page on cache lines ...says hints can prepare, discard, or evict cache lines (also called buffers?). So are hints just instructions that relate to cache lines?

Thank you

Answer 1

A hint is part of the operation of an instruction that may not be implemented in the manner described. It may not be implemented at all or it may be implemented in a different way. What exactly the hint does may depend on the specific circumstances in which the instruction is executed. Generally speaking how a hint is implemented doesn't affect the architectural state of the CPU. For cache related hints this means that what exactly ends up in the cache may vary, although for the current processor at least the cache will remain in a consistent state. (Other processors may see memory accesses made by the current processor in an inconsistent order with respect to the normal x86 memory ordering rules, as some hints can violate these rules.)

For example, non-temporal hints tell the processor to avoid using up space in the cache for the given memory reference. They are normally used because the programmer believes that the location in memory isn't going to be accessed again by the CPU, so using the cache would be a waste of space. Writing to video memory is a common example of this, as video memory is almost always used by programs as "write-only" memory.

In practice, non-temporal hints can vary a lot in their operation, depending on the particular CPU, whether or not write-combining (WC) memory used, whether not it's a read or a write, and the specific instruction. See BeeOnRope's answer to a question about non-temporal loads and normal memory for some of the possible differences. Also note that given the asynchronous nature of the caches, the exact behaviour of anything cache related is hard to nail down as prefetching and the actions of other processors can easily evict or bring in cache lines unexpectedly.