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I'm trying to dump the value of make variables to a file for further processing.
So far, I've been able to print the values to the command line using the following rule:
print-%:
@echo '$*=$($*)'
Which you call with the command line
make print-VAR
I really don't want it on stdout, but printed to a file. The GNU Make "file" function seems like the thing I should be using: http://www.gnu.org/software/make/manual/html_node/File-Function.html#File-Function
The page jumps into a complex example right away though, so I've implemented the following but can't seem to get it to work: it prints the @echo to stdout, but when I look in my directory there is no output.txt file.
printf-%:
@echo '$*=$($*)'
$(file > output.txt,$($*))
What am I missing?
EDIT: Well, looks like I can just use
@echo '$($*)' > output.txt
to do what I want, but that still doesn't explain why my file call wasn't working.
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The call function is unique in that it can be used to create new parameterized functions. You can write a complex expression as the value of a variable, then use call to expand it with different values. The syntax of the call function is: $(call variable , param , param ,…)
Also you can just type make if your file name is makefile/Makefile . Suppose you have two files named makefile and Makefile in the same directory then makefile is executed if make alone is given. You can even pass arguments to makefile.
The file function allows the makefile to write to or read from a file. Two modes of writing are supported: overwrite, where the text is written to the beginning of the file and any existing content is lost, and append, where the text is written to the end of the file, preserving the existing content.
The file function allows the makefile to write to or read from a file. Two modes of writing are supported: overwrite, where the text is written to the beginning of the file and any existing content is lost, and append, where the text is written to the end of the file, preserving the existing content.
Include all the source files in the makefile. Set the rule and dependencies according to your project needs. Simply run make command. Damn it! This will help you to avoid your big and gusty way of writing compiler commands.
We can also use variables in the Makefile to generalise Makefile. In this examples we are writing Makefile using variables and clean target name to remove all object (.o extension files) and binary file (main). sh-4.3$ make gcc main.c misc.c -o main sh-4.3$ ./main Hello, World.
Command make is used to compile program through Makefile, since there are only one target all in the Makefile, so we do not need to mention target name because first target is got compiled automatically. sh-4.3$ make gcc main.c misc.c -o main sh-4.3$ ./main Hello, World. Body of myFunc function. sh-4.3$
Two Responses from comments section:
1) To get the functionality desired, just redirect the "@echo" statement to a file
printf-%:
@echo '$*=$($*)' > output.txt
2) The reason the file function did not work is that it is a feature of Make v4.0 and newer, not 3.8, which was the version I was using.
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