Invoking the Makefile of parent directory

Question

I have a project with the following directory structure:

foo/
foo/Makefile
foo/bar/

My goal is to add a file foo/bar/Makefile, so that if I invoke make in foo/bar, the Makefile of the parent directory will be used. It's kind of an inverted recursive Makefile structure (I want every Makefile to invoke the parent directory until it reaches the project root).

Symlinking fails since invoking it from the wrong directory breaks all relative paths:

$ ln -s ../Makefile foo/bar/Makefile
$ make -C foo/bar
[error]

The only solution I have found is to write a Makefile which captures all of the targets that I am interested in and invokes the parent directory with that target:

$ cat foo/bar/Makefile
all clean:
    $(MAKE) -C .. $@

This is laborious and prone to break. Is there a more elegant solution?

Justification

The project is a large LaTeX document which contains multiple subdirectories for .tex files for Chapters, Figures, etc. I want to be able to invoke make from any one of these directories to build the document.

Answer 1

Thanks Etan Reisner for point out the match-anything rule. This Makefile will capture all targets and pass them up to the parent Makefile:

all:
    @make -C .. $@
%:
    @make -C .. $@

Note that it was necessary to provide a default all rule in addition to the match-anything rule, as otherwise make would complain if invoked with no arguments: make: *** No targets. Stop.