OSX Mavericks causes "cannot specify -o when generating multiple output files"

Question

Since I installed mavericks on my mac, I can't compile some of my programs.

**clang: error: cannot specify -o when generating multiple output files **

The makefile is :

SHELL = /bin/sh
CC = gcc
CFLAGS = -Wall -O3 -funroll-all-loops
EXEC = program
SRC = $(EXEC).c file1.c file2.c file3.c file4.c
OBJ = $(SRC:.c=.o)
LIB = $(SRC:.c=.h)

all: $(EXEC)

$(EXEC): $(OBJ) $(LIB)
    $(CC) -o $@ $^ $(LDFLAGS) -lm

%.o: %.c $(LIB)
    $(CC) -o $@ -c $< $(CFLAGS)

• gcc is redirected to clang, but I don't know if this causes the described error.
• gcc is installed
• I don't know how to cancel this redirection to test again.
• I saw this post : Makefile; gcc not working? Believe Mavericks is responsible but I don't really understand the problem and its resolution

Thanks for your attention

Answer 1

Remove $(LIB) from the line:

$(EXEC): $(OBJ) $(LIB)

The way LIB is defined, it has the value program.h file1.h file2.h file3.h file4.h. This has two effects.

First, it says that $(EXEC), which is program, depends on the .h files. However, program depends directly only on the .o files. program does not directly use the .h files in its build, so the dependencies for program should not include the .h files.

Second, the $^ in the command says to list all the files that the target depends on. This passes all the .o and .h files to the compiler. When the compiler sees several .h files listed, it figures that several source files will be compiled, and therefore several object files will be produced.

When you remove $(LIB) from the dependencies in this rule, the .h files will not be listed in the command. Then the compiler will see only several .o files, so it will know it is linking several objects into one executable and will not attempt to compile source files.