timing constraints

Question

I'm designing a ULPI interface for communicating with an USB chip.
But I have run into some problems regarding timing constraints.

Data is output at the rising edge of the clock, and sampled at the falling edge.

I can see (using Post-Route) that there is about 6ns "best case achievable delay" from clock rising edge to data out is valid.

If I want a smaller delay, should I rewrite my code and for example delay my clock until the rising edge fits with data out?

I know above solution is probably not good, since it will be both fpga device and route dependent... But what other options are there?

Answer 1

Is your data output register packed into an IO register? The constraint in a UCF is: INST "some_ff" IOB = TRUE; Or, you can use the map option -pr b which will pack inputs and outputs ([b]oth) into io registers.

This has 2 effects:

1. Locks down timing between the IO pin and the first/last D/Q pin of the FF (build to build consistency)
2. Maximizes clock-to-out performance (you can't get your Q any closer to the output pin).

Edit: The above recommendation applies to Xilinx toolchains. Other vendors likely have similar architectures, but the arguments/controls required to invoke the option differs.