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New posts in fpga
Doxygen alternative for Verilog, SystemVerilog?
Sep 25, 2018
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doxygen
fpga
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How to enable SD card with Nios II MMU and Linux 4.9
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Linux PCIe DMA Driver (Xilinx XDMA)
Nov 12, 2022
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FPGA TCP implementation [closed]
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iCEstick + yosys - using the Global Set/Reset (GSR)
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In VHDL ..... how to count leading zeros of vector?
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FPGA Place & Route
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Weird XNOR behaviour in VHDL
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Difference between unsigned and std_logic_vector
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Should you remove all warnings in your Verilog or VHDL design? Why or why not?
Apr 25, 2022
verilog
vhdl
fpga
intel-fpga
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What is the simplest way to transmit a signal over MGT of Xilinx FPGA?
Nov 06, 2022
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Open Source OCR system for FPGA [closed]
May 22, 2022
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ocr
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hdl
Linux driver DMA transfer to a PCIe card with PC as master
Apr 16, 2016
linux-kernel
linux-device-driver
fpga
dma
pci-e
Triggering signal on both edges of the clock
Jun 19, 2022
verilog
clock
fpga
How to send data to AXI-Stream in Zynq from software tool?
Sep 06, 2022
linux
arm
fpga
xilinx
zynq
what is the difference between slice registers and slice LUTs in Xilinx FPGA?
May 31, 2022
fpga
xilinx
Resources for learning Verilog [closed]
Feb 20, 2017
microcontroller
verilog
fpga
VHDL: creating a very slow clock pulse based on a very fast clock
Mar 01, 2019
vhdl
clock
fpga
Is it possible to create a simulation waveform from yosys output
Aug 30, 2022
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simulation
fpga
yosys
Ideas for a flexible/generic decoder in VHDL
Mar 10, 2022
vhdl
fpga
xilinx
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