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In a makefile, can I call a rule from another rule?
Similar to:
rule1: echo "bye" rule2: date rule3: @echo "hello" rule1 
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A rule appears in the makefile and says when and how to remake certain files, called the rule's targets (most often only one per rule). It lists the other files that are the prerequisites of the target, and the recipe to use to create or update the target.
When you type make or make [target] , the Make will look through your current directory for a Makefile. This file must be called makefile or Makefile . Make will then look for the corresponding target in the makefile. If you don't provide a target, Make will just run the first target it finds.
We will now learn the rules for Makefile. In the above code, the arguments in brackets are optional and ellipsis means one or more. Here, note that the tab to preface each command is required. A simple example is given below where you define a rule to make your target hello from three other files.
The variable $@ represents the name of the target and $< represents the first prerequisite required to create the output file.
Either use dependencies or recursive making to connect from one rule to another.
Dependencies would be done like this (though the order will be different):
rule1: echo "bye" rule2: date rule3: rule1 @echo "hello" Recursive make would be done like this (though it does involve a subprocess):
rule1: echo "bye" rule2: date rule3: @echo "hello" $(MAKE) rule1 Neither is perfect; indeed, with recursive make you can get into significant problems if you build a loop. You also probably ought to add a .PHONY rule so as to mark those rules above as synthetic, so that a stray rule1 (etc.) in the directory won't cause confusion.
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