I have a directory (root_dir
), that contains a number of sub-directories (subdir1, subdir2, ...
).
I want to run the make
in each directory in root_dir
, using a Makefile placed in it. (Obviously supposed that each of subdir...
has inside its own Makefile).
So there are essentially two questions:
make
for each of the directories inside a make file?As I know in order to run make
in a specific directory I need to do the following:
$(MAKE) -C subdir
# Register all subdirectories in the project's root directory. SUBDIRS := $(wildcard */.) # Recurse `make` into each subdirectory. $(SUBDIRS): FORCE $(MAKE) -C $@ # A target without prerequisites and a recipe, and there is no file named `FORCE`.
The mkdir command in Linux/Unix allows users to create or make new directories. mkdir stands for “make directory.” With mkdir , you can also set permissions, create multiple directories (folders) at once, and much more.
A subdirectory is a type of website hierarchy under a root domain that uses folders to organize content on a website. A subdirectory is the same as a subfolder and the names can be used interchangeably.
Files are organized by storing related files in the same directory. In a hierarchical file system (that is, one in which files and directories are organized in a manner that resembles a tree), a directory contained inside another directory is called a subdirectory.
There are various problems with doing the sub-make inside a for loop in a single recipe. The best way to do multiple subdirectories is like this:
SUBDIRS := $(wildcard */.) all: $(SUBDIRS) $(SUBDIRS): $(MAKE) -C $@ .PHONY: all $(SUBDIRS)
(Just to point out this is GNU make specific; you didn't mention any restrictions on the version of make you're using).
ETA Here's a version which supports multiple top-level targets.
TOPTARGETS := all clean SUBDIRS := $(wildcard */.) $(TOPTARGETS): $(SUBDIRS) $(SUBDIRS): $(MAKE) -C $@ $(MAKECMDGOALS) .PHONY: $(TOPTARGETS) $(SUBDIRS)
Try this :
SUBDIRS = foo bar baz subdirs: for dir in $(SUBDIRS); do \ $(MAKE) -C $$dir; \ done
This may help you link
Edit : you can also do :
The simplest way is to do:
CODE_DIR = code .PHONY: project_code project_code: $(MAKE) -C $(CODE_DIR)
The .PHONY rule means that project_code is not a file that needs to be built, and the -C flag indicates a change in directory (equivalent to running cd code before calling make). You can use the same approach for calling other targets in the code Makefile.
For example:
clean: $(MAKE) -C $(CODE_DIR) clean
Source
If you love us? You can donate to us via Paypal or buy me a coffee so we can maintain and grow! Thank you!
Donate Us With