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I want to disable builtin rules and variables as per passing the -r and -R options to GNU make, from inside the make file. Other solutions that allow me to do this implicitly and transparently are also welcome.
I've found several references to using MAKEFLAGS, and had similar problems.
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The variable $@ represents the name of the target and $< represents the first prerequisite required to create the output file.
The third variable used in this file is OBJS. In this makefile, this variable specifies all the object files required to construct the main program.
A rule appears in the makefile and says when and how to remake certain files, called the rule's targets (most often only one per rule). It lists the other files that are the prerequisites of the target, and the recipe to use to create or update the target.
Implicit rules tell make how to use customary techniques so that you do not have to specify them in detail when you want to use them. For example, there is an implicit rule for C compilation. File names determine which implicit rules are run. For example, C compilation typically takes a . c file and makes a .o file.
Disabling the built-in rules is done by writing an empty rule for .SUFFIXES:
.SUFFIXES: Having erased the built-in rules, I'm not sure that erasing the built-in variables helps you much more than just remembering to set them yourself or not use them, but you could use something like
$(foreach V, $(shell make -p -f/dev/null 2>/dev/null | sed -n '/^[^:#= ]* *=/s/ .*//p'), $(if $(findstring default,$(origin $V)),$(eval $V=))) ...which is admittedly fairly crazy. If there is a way to get a list of the defined variables from within make (instead of shelling out to another make), it would be viable. As it is, it's not really much better than
CC= CXX= # etc, for each likely built-in variable If you love us? You can donate to us via Paypal or buy me a coffee so we can maintain and grow! Thank you!
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