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I am using a GNU-make Makefile to build a C project with several targets (all, clean, and a few project specific targets). In the process of debugging, I would like to append some flags to a single build without permanently editing the Makefile (e.g. add debugging symbols or set a preprocessor flag).
In the past, I have done that as follows (using the debugging symbols example):
make target CFLAGS+=-g Unfortunately, this is not appending to the CFLAGS variable, but instead, clearing it and stopping it from compiling. Is there a clean way of doing this without defining some sort of dummy variable appended to the end of CFLAGS and LDFLAGS?
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makefile Variables Appending Text To an Existing VariableThe += operator is a common extension that adds the specified content to the end of the variable, separated by a space. Variable references in the right-hand side will be expanded if and only if the original variable was defined as a simply-expanded variable.
The variable $@ represents the name of the target and $< represents the first prerequisite required to create the output file.
+= is used for appending more text to variables e.g. objects=main.o foo.o bar.o. objects+=new.o. which will set objects to 'main.o foo.o bar.o new.o' = is for recursively expanded variable.
It should be CFLAGS := -Wall -Wextra $(CFLAGS) , the difference is that CFLAGS is explicitly appended. So for example, you may set -Og , but user don't want optimization and passes CFLAGS=-O0 on command line. By using CFLAGS += -Og your -Og will take over the user provided value.
Check out the override directive. You will probably need to modify the makefile once, but it should do what you want.
Example makefile:
override CFLAGS += -Wall app: main.c gcc $(CFLAGS) -o app main.c Example command lines:
$ make gcc -Wall -o app main.c $ make CFLAGS=-g gcc -g -Wall -o app main.c If you love us? You can donate to us via Paypal or buy me a coffee so we can maintain and grow! Thank you!
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