make always rebuild

Question

My Makefile is:

OBJS = b.o c.o a.o
FLAGS = -Wall -Werror
CC = gcc

test: $(OBJS)
    $(CC) $(FLAGS) $(OBJS) -o test
b.o: b.c b.h
    $(CC) $(FLAGS) -c b.c
a.o: a.c b.h c.h
    $(CC) $(FLAGS) -c a.c
c.o: c.c c.h
    $(CC) $(FLAGS) -c c.c
clean:
    rm a
    rm *.o
all: test

If I do make then make again, it always rebuilds 'test'. Why does it do this?

Even if i do: make a.o it rebuilds... Im on linux if that helps.

In windows if I change 'test' by 'test.exe' and '-o test' by '-o test.exe', it works fine. So I guess that for some reason 'make' in my linux cant check the datestamps of my files in the directory.

I FIXED IT! The .c were created in Windows. I opened all .c and .h in vi, and without doing nothing save changes, and all worked. I think that the datestamp thing was fixed doing this.

Answer 1

Your first rule is:

test: $(OBJS)

That means if a file named 'test' doesn't exist, the rule should run and create it. Since 'test' never exists (that rule doesn't actually create a file named 'test'), it runs every time. You should change 'test' to 'a', the actual output of that rule

For future reference, if a rule doesn't actually create the thing on the left-hand side, you should mark it with:

.PHONY: test