Calling make from within a makefile

Question

I have a Makefile which works perfectly called from a new shell, i.e.:

make -C /dir/

However, if I call this Makefile from another Makefile, it fails due to some complicated dependency issues. Make clearly has knowledge of the nested calls, evident by the print of make[1]: etc, and I suspect make is somehow sharing variables with its child process.

Is there anyway to call a clean make from within a Makefile? If my build works from a clean shell, it should be possible to call it from another Makefile without addressing the horrors inside the script! :)

Thanks!

Answer 1

make indeed shares some of its environment when it is recursively called. As suggested in https://www.gnu.org/software/make/manual/html_node/Options_002fRecursion.html#Options_002fRecursion, you might want to write your recursive call that way:

sub-make:
        $(MAKE) -C /dir/ MAKEFLAGS=

and see if it helps. You can also control the variables that are exported to the sub-make by using export and unexport directives (https://www.gnu.org/software/make/manual/html_node/Variables_002fRecursion.html#Variables_002fRecursion)

Answer 2

It was a few environment variables in the caller make that broke the callee make (CFLAGS etc...)

My solution was to diff the environment at a clean shell and from the point of call. I then manually added the problem variables to a list and created some save_env/restore_env scripts.

Thanks!