Is there a way to tell automake not to interpret part of the Makefile.am?
Specifically, I am trying to encode a Makefile conditional in a Makefile.am. As other people have noticed, this doesn't work because automake interprets the endif construct.
Is there any way to escape or quote strings in Makefile.am files so that automake copies them verbatim into the destination Makefile? Specifically I don't want it to interpret the endif in something like:
ifeq "$(SOMEVAR)" ""
SOMEVAR="default_value"
endif
The reason automake does conditionals is because some dinosaur makes don't. That said, if you really must do this, you could define your snippet as a variable in configure.ac
and AC_SUBST
it into your Makefile
. That way, automake won't get a chance to see it. Remember to use AM_SUBST_NOTMAKE
to avoid creating a line like FOO = @FOO@
.)
dnl In configure.ac:
snippet='
ifeq ($(somevar),Y)
foo
endif
'
AC_SUBST([snippet])
AM_SUBST_NOTMAKE([snippet])
and:
## In Makefile.am:
@snippet@
I sincerely hope there's a better way than this.
I managed to find a different solution. You can put your to-be-escaped bits in a separate file and then do:
$(eval include $(srcdir)/Include.Makefile)
Since automake doesn't understand $(eval
it just leaves the entire line intact. Thus you can put whatever you want into the other file and GNU make will happily read it. Note you can't just use include
directly since Automake does understand that and will go into the other file.
The simplest way to do so is to insert a space before the ifdef
, ifeq
, ifneq
, else
and endif
. That way, these keywords are not recognized by the automake parser. Be sure to insert a space, it won't work with a tab.
source: https://patchwork.kernel.org/patch/6709921/
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