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First, some context: I'm working with a pre-C11, inline-asm-based atomic model, but for the purposes of this I'm happy to ignore the C aspect (and any compiler barrier issues, which I can deal with separately) and consider it essentially just an asm/cpu-architecture question.
Suppose I have code that looks like:
various stores
barrier
store flag
barrier
I want to be able to read flag from another cpu core and conclude that the various stores were already performed and made visible. Is it possible to do so without any kind of memory barrier instruction on the loading side? Clearly it's possible at least on some cpu architectures, for example x86 where an explicit memory barrier is not needed on either core. But what about in general? Does it vary widely by cpu arch whether this is possible?
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The memory barrier instructions halt execution of the application code until a memory write of an instruction has finished executing. They are used to ensure that a critical section of code has been completed before continuing execution of the application code.
Memory barriers are typically used when implementing low-level machine code that operates on memory shared by multiple devices. Such code includes synchronization primitives and lock-free data structures on multiprocessor systems, and device drivers that communicate with computer hardware.
A write memory barrier gives a guarantee that all the STORE operations specified before the barrier will appear to happen before all the STORE operations specified after the barrier with respect to the other components of the system.
Memory barriers, or fences, are a set of processor instructions used to apply ordering limitations on memory operations.
If a CPU were to reorder the loads, your code would require a load barrier in order to work correctly. There are plenty of architectures that do such reordering; see the table in Memory ordering for some examples.
Thus in the general case your code does require load barriers.
x86 is not very typical in that it provides pretty stringent memory ordering guarantees. See Who ordered memory fences on an x86? for a discussion.
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