How to manually call another target from a make target?

Question

I would like to have a makefile like this:

cudaLib :
    # Create shared library with nvcc

ocelotLib :
    # Create shared library for gpuocelot

build-cuda : cudaLib
    make build

build-ocelot : ocelotLib
    make build

build :
    # build and link with the shared library

I.e. the *Lib tasks create a library that runs cuda directly on the device, or on gpuocelot respectively.

For both build tasks I need to run the same build steps, only creating the library differs.

Is there an alternative to running make directly?

make build

Kind of a post-requisite?

Answer 1

^{Note: This answer focuses on the aspect of a robust recursive invocation of a different target in a given makefile.}

To complement Jack Kelly's helpful answer, here's a GNU makefile snippet that demonstrates the use of $(MAKE) to robustly invoke a different target in the same makefile (ensuring that the same make binary is called, and that the same makefile is targeted):

# Determine this makefile's path. # Be sure to place this BEFORE `include` directives, if any. THIS_FILE := $(lastword $(MAKEFILE_LIST))  target:     @echo $@  # print target name     @$(MAKE) -f $(THIS_FILE) other-target # invoke other target  other-target:     @echo $@ # print target name 

Output:

$ make target  target other-target 

Using $(lastword $(MAKEFILE_LIST)) and -f ... ensures that the $(MAKE) command uses the same makefile, even if that makefile was passed with an explicit path (-f ...) when make was originally invoked.

---

Note: While GNU make does have features for recursive invocations - for instance, variable $(MAKE) specifically exists to enable them - their focus is on invoking subordinate makefiles, not on calling a different target in the same makefile.

That said, even though the workaround above is somewhat cumbersome and obscure, it does use regular features and should be robust.

Here is the link to the manual section covering recursive invocations ("sub-makes"):

• Recursive Use of make

Answer 2

Most versions of make set a variable $(MAKE) that you can use for recursive invocations.